The present embodiments relate to semiconductor circuits and are more particularly directed to a drive circuit and a drain extended transistor for use in that circuit.
Semiconductor devices are prevalent in all aspects of electronic circuits, and such circuits sometimes include so-called mixed signal technology that uses both analog devices (e.g., amplifiers) and digital devices (e.g., logic circuits). In mixed signal technology, typically the voltage supply used by the analog devices is higher than that used by the digital devices, where the voltage supply used by the digital devices is sometimes referred to as the core voltage. As a result, some type of voltage level shifting is implemented to couple the two different circuits to supply or to trigger one circuit (e.g., analog) based on an input level of the other circuit (e.g., digital). In the prior art, such level shifting is typically achieved by either using a dual gate oxide process in a gate drive configuration as detailed below, or it may be achieved by using several drain extended transistors in a so-called cascode configuration. Both of these techniques have additional costs associated with them.
By way of further background to the preceding, FIG. 1 illustrates a schematic of a prior art drive circuit 10 that is implemented in a mixed technology system and using a dual gate oxide process, where the process is so named because some transistors in the system have one gate oxide thickness while other transistors in the same system have a different gate oxide thickness; hence, there are “dual” thicknesses. Looking to circuit 10 in detail, it includes a gate drive stage 20 and an inverter stage 40. Gate drive stage 20 includes a p-channel transistor 22 cross-coupled to a p-channel transistor 24 in that the source of both of transistors 22 and 24 is connected to Vdd and the gate of each of p-channel transistors 22 and 24 is connected to the drain of the opposing p-channel transistor. Note that the value of Vdd is that from the analog portion of the mixed technology system and, thus, may be quite high as compared to the voltage supply of the digital portion or core, referred to herein as VDDC. For example, in contemporary devices, Vdd may be in the range of 20 to 80 volts while VDDC may be in the range of 1 to 5 volts. Continuing with the circuit connectivity, the drain of p-channel transistor 22 is connected to a node 20N1 which is also connected to the drain of an n-channel transistor 26, and the source of n-channel transistor 26 is connected to ground. Comparably, the drain of p-channel transistor 24 is connected to a node 20N2 which is also connected to the drain of an n-channel transistor 28, and the source of n-channel transistor 28 is connected to ground. A low side drive logic block 30 provides a signal to an input node 32 which is connected to the gate of n-channel transistor 26 and through an inverter 34 to the gate of n-channel transistor 28. Looking to inverter stage 40, it includes a p-channel transistor 42 having its source connected to Vdd, its drain connected to an output node 44, and its gate connected to node 20N2 (i.e., the drains of p-channel transistor 24 and n-channel transistor 28). Inverter stage 40 also includes an n-channel transistor 46 having its source connected to ground, its drain connected to output node 44, and its gate connected to input node 32. Lastly, note that p-channel transistors 22, 24, and 42 are all formed with relatively thick gate oxides, such as on the order of 500 to 1,000 Angstroms thick. N-channel transistors 26, 28, and 46, however, may have thinner gate oxides, such as on the order of 40 to 200 Angstroms thick. Thus, a dual gate oxide process is implemented so as to accommodate both the thick and thin gate oxides, where the former are required for reasons better understood below.
The general operation of drive circuit 10 will be readily appreciated by one skilled in the art, but is described briefly here so as to focus on certain aspects for contrast to the preferred embodiments detailed later. In general, a data state at input node 32 causes a complementary data state at output node 44. As a first example of operation, if a ground voltage is applied by block 30 to input node 32, then n-channel transistors 26 and 46 are disabled, while inverter 34 outputs a voltage of VDDC because n-channel transistors 26, 28, and 46 may operate at the core voltage levels as are also provided by low side drive logic block 30. Thus, the voltage of VDDC is applied to the gate of n-channel transistor 28, thereby enabling it and thus connecting node 20N2 to ground. The ground potential at node 20N2 is connected to the gate of p-channel transistor 42, thereby enabling it and bringing output node 44 to Vdd. At the same time, the ground potential at node 20N2 is connected to the gate of p-channel transistor 22, thereby enabling it and bringing node 20N1 to Vdd. The Vdd at node 20N1 is connected to the gate of p-channel transistor 24, thereby maintaining it in a disabled state. From the preceding, therefore, an overall function of circuit 10 is that a ground voltage at input node 32 causes a voltage of Vdd at output node 44. One skilled in the art may readily appreciate the complementary operation as well, that is, a voltage of VDDC at input node 32 causes a ground voltage at output node 44.
With an understanding of the preceding, a drawback of circuit 10 may be appreciated in that the circuit necessitates the use of thick gate oxide p-channel transistors. Specifically, note in the first example of operation above that p-channel transistor 22 is enabled. As a result, it has Vdd at its source and conducts that to its drain, while at the same time it has a ground potential at its gate. Thus, since Vdd is relatively large in this example (as compared to the digital core logic supply voltage), then a large voltage difference exists as between this same voltage in the channel of the transistor and the ground voltage at its gate. As known in the art, such a large voltage may cause a breakdown of the device, particularly in the areas where the source or drain diffused regions are near the gate sidewalls. To avoid such a breakdown, the above-introduced thicker gate oxide is used in this transistor, and for similar reasons it is also used in p-channel transistors 24 and 42. At the same time, n-channel transistors 26, 28, and 46 do not necessitate a thick gate oxide and, hence, they are constructed using a thinner gate oxide. Accordingly, there is a dual gate oxide process required in that one thickness is sufficient for the n-channel transistors while another in this configuration is necessitated for the p-channel transistors. This process provides added expense and complexity, and as is well-known in the art these additions in device fabrication are unfavorable if they may be satisfactorily avoided.
By way of further background, another technique used with mixed signal technology is the cascoding of so-called drain extended MOS (“DEMOS”) transistors, where a single one of such transistors is now introduced in connection with FIGS. 2a and 2b. Specifically, FIG. 2a illustrates a cross-sectional view, and FIG. 2b illustrates a plan view, of a prior art DEMOS transistor 50. Transistor 50 is a p-channel DEMOS device, formed at a surface of typically lightly-doped semiconductor substrate 52. This example structure, as typical in the art for integrated circuits constructed according to complementary MOS (CMOS) technology, is formed according to a conventional twin-well process, in which an n-type well region 54 and a p-type well region 56 are formed at the surface of substrate 52. Both in the illustrated location and elsewhere in the integrated circuit, wells 54 and 56 serve as the body region for p-channel MOS and n-channel MOS transistors, respectively, and as such are typically relatively lightly doped. Field oxide structures 58a and 58b are formed and isolate conductive regions from one another. Although not shown, doped regions may be disposed beneath field oxide structures 58a and 58b to serve as so-called “channel stops” to enhance the isolation provided by field oxide regions 58a and 58b. 
Turning to the active portions of DEMOS transistor 50, they are formed by self-aligned ion implantation at the surface of wells 54 and 56. In this example, a gate electrode 60 is a patterned layer of polysilicon, metal, silicide-clad polysilicon, or another known conductive material suitable for use as a transistor gate, and disposed over a gate oxide layer 61. Sidewall insulating regions may be disposed along the edges of gate electrode 60. A source region 62 is a heavily-doped p-type region that is formed by ion implantation in a self-aligned manner relative to gate electrode 60 and field oxide structure 58a at the surface of n-well 54. Further, a drain region 64 is a heavily doped p-type region formed by ion implantation into the surface of p-well 56, self-aligned relative to field oxide structure 58b and preferably using the same implant or implants used to form source region 62. A backgate contact region 66 is a heavily-doped n-type region formed at a selected location of n-well 54.
Completing the remaining structure of transistor 50, an overlying insulator layer 68 is disposed over all of the above-described underlying structures, including gate electrode 60, field oxide structures 58a and 58b, and source, drain, and backgate contact regions 62, 64, and 66, respectively. Contact openings are etched through insulator layer 68 at selected locations, and metal is then located within the openings and etched to form BGC(“backgate”), SC (“source”), and DC (“drain”) conductors, as shown in FIGS. 2a and 2b. In addition, also shown in FIG. 2b (but not in FIG. 2a due to the location of the cross-section taken across FIG. 2b to provide FIG. 2a) is a gate conductor GC (“gate”), which extends downward to contact, for purposes of applying a potential to, gate electrode 60.
As mentioned above, transistor 50 of FIGS. 2a and 2b is a drain-extended device. This drain extension is implemented in part by field oxide structure 58b that is located to form drain region 64 as shown and onto which gate electrode 60 overlaps. Also in connection with the drain-extension aspects, and as shown in FIG. 2a, p-well 56 extends inwardly from and relative to drain region 64 toward the transistor channel and beyond field oxide structure 58b, and an interface IF exists between p-well 56 and n-well 54. For sake of later contrast, a dashed line DL1 is shown in FIGS. 2a and 2b at the location where interface IF terminates under gate oxide 61. The operation and effect with respect to this extension is explored immediately below.
When transistor 50 is turned on by the application of a negative gate-to-source voltage, via gate conductor GC (and gate electrode 60) relative to source conductor SC (and source region 62), the majority carrier holes for the PMOS device are attracted to and thereby create an inversion channel in the n-type material of n-well 54 under gate oxide 61, where furthermore the holes conduct from source region 62 toward the lower voltage at drain region 64 along this inversion channel. Upon reaching interface IF, that is, upon encountering p-well 56, the inversion channel is no longer present, but the holes continue to drift toward drain region 64. As such, the portion of p-well 56 between drain region 64 and the channel region formed in n-well 54 is referred to as the “drift region” of the DEMOS device, and is shown in FIG. 2a as drift region DFT.
Consider now the case where source conductor SC (and source region 62) and gate conductor GC (and hence gate electrode 60) are connected to a relatively large Vdd voltage, such as on the order of 50 volts, while drain conductor DC (and drain region 64) is connected to ground. In this instance, the gate-to-source voltage is zero and the gate voltage repels the p-type majority carrier holes away from the channel area beneath gate oxide 61, thereby preventing conduction between the source and drain regions of the device. At this same time, however, note that the voltage difference, between Vdd at gate conductor GC and ground at drain conductor DC, is considerable, given that Vdd in this example is relatively large. As a result, in prior art devices without an extended drain region as is provided by p-well 56, this difference could cause a breakdown of gate oxide 61, particularly if drain region 64 were closely self-aligned, as it is in the prior art, to the edge of gate electrode 60. In contrast, however, in effect when transistor 50 is not conducting, p-well 56 causes a voltage gradient GR across the resistive body of that well, thereby reducing the effective difference of voltage between gate electrode 60 and the channel in the direction toward drain region 64. As a result, the chance of breakdown of gate oxide 61 is diminished.
Given the preceding, one skilled in the art will appreciate the construction and use for a DEMOS transistor, and recall further that above it was noted that such a device may be cascoded by using multiple ones of these devices in mixed signal applications, using therefore the cascoded devices to withstand the larger voltage swing from the analog voltage supply. While such an approach is acceptable in various applications, it has certain drawbacks, such as added complexity, larger overall circuit size, and cost increase.
In view of the above, there arises a need to address the drawbacks of the prior art, as is achieved by the preferred embodiments described below.